1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly relates to a semiconductor device including a vertical semiconductor element which has a super junction structure and a method for manufacturing the same.
2. Description of the Related Art
In recent years, reduction in thickness and weight of electronic apparatuses, such as a liquid crystal television, a plasma television, and an organic electroluminescent television, has been strongly requested. Concomitant with this trend, reduction in size and improvement in performances of electric power devices embedded in electronic apparatuses have also been strongly requested.
Accordingly, in power semiconductor elements used as electric power apparatuses, in particular, in a vertical type metal oxide semiconductor field effect transistor (hereinafter referred to as “MOSFET”), an improvement in performances, such as an increase in withstand voltage, an increase in amount of current, a decrease in loss, an increase in speed, and an increase in fracture resistance, has been aggressively carried out.
The on-resistance and the withstand voltage of a vertical MOSFET strongly depend on an impurity concentration of an n-type semiconductor region which functions as a conductive layer of the MOSFET. In order to decrease the on-resistance, it is necessary to increase the impurity concentration of the n-type semiconductor region. However, in order to ensure a desired withstand voltage, it is not allowed to increase the impurity concentration of the n-type semiconductor region to a certain level or more.
The withstand voltage and the on-resistance have a trade-off relationship. As one method to overcome the relationship mentioned above, a vertical MOSFET having a super junction structure has been proposed in which p-type semiconductor regions and n-type semiconductor regions are arranged in a stripe pattern in a region in which the withstand voltage has to be ensured (for example, see Japanese Unexamined Patent Application Publication No. 7-7154). In this vertical MOSFET (hereinafter referred to as “super junction vertical MOSFET”), a current is allowed to flow in the n-type semiconductor regions each functioning as a conductive layer in an ON state, and in an OFF state, the p-type semiconductor regions and the n-type semiconductor regions are completely depleted, so that the withstand voltage can be ensured.